The present invention relates to semiconductor devices, and more particularly to a system and method for compensating for parasitics caused by elements added to semiconductor devices for ESD protection.
The technology of semiconductor design has advanced by decreasing circuit element dimensions and increasing circuit densities. The decrease in circuit element dimensions has resulted in the decrease of the thickness of insulating layers, such as gate oxide layers, with an associated decrease in the range of operating voltages. This scaling down of the insulating layers makes the semiconductor devices more sensitive to voltages outside of operating parameters (both overvoltages and undervoltages). An overvoltage or undervoltage can damage or destroy a semiconductor device by shorting through the thin insulating layers in the device.
A common type of damaging voltages outside of operating parameters is electrostatic discharge (ESD). A semiconductor device, such as a CMOS device, may be subjected to ESD merely by being handled by a person. The input and output terminals of a semiconductor device are easily touched, and thus are very susceptible to damage from ESD. To protect against damage from ESD, the input and output terminals of semiconductor devices typically include ESD protection circuitry. This ESD protection circuitry is designed to direct the charge (i.e. current) from an ESD event either to a power or a ground bus in the device. Although the operating voltages for a semiconductor circuit decrease with decreasing circuit element dimensions, the size of a typical ESD event remains the same. As a result, ESD protection circuitry is not typically scaled down with the rest of the circuit elements on a semiconductor device so that the same level of ESD protection can exist for the semiconductor device.
Unfortunately, ESD protection circuitry at an input or output (I/O) terminal of a semiconductor device adds parasitics (e.g. a parasitic capacitance) onto the signal lines of the I/O terminal. FIG. 1A is a block diagram of an I/O terminal 100 for a semiconductor device utilizing a conventional ESD protection circuit. I/O terminal 100 includes an I/O pad 110 coupled to ESD protection circuitry 120 at a node N1. The parasitic capacitance of ESD protection circuitry 120 is modeled as a capacitor 122. This parasitic capacitance (the impedance of ESD protection circuitry 120) forms a low pass filter (described in more detail below) with the effective signal source or load impedance. This low pass filter effect is unacceptable in high-speed circuit designs, such as gigabit Ethernet or Synchronous Optical Network (SONET) applications.
The impedance of a capacitor, represented as a Laplace transform, is 1/s*C. The impedance of ESD protection circuitry 120 (e.g. 1/s*C122) decreases as the frequency of the signal (s=jxcfx89) applied to I/O pad 110 increases. Because of voltage division between the signal source impedance and the impedance of ESD protection circuitry 120, the signal strength at I/O pad 110 decreases with the decrease in impedance of ESD protection circuitry 120. The magnitude and phase of the frequency response of the effect of ESD protection circuitry 120 on the signal at I/O pad 110 are shown in FIGS. 1B and 1C, respectively. As shown in FIG. 1B, ESD protection circuitry 120 causes attenuation of signals applied at I/O pad 110 having frequency greater than roll-off frequency F1. In this way, ESD protection circuitry 120 has the effect of a low pass filter. As the circuit element dimensions of the semiconductor device decrease (i.e. the internal semiconductor device circuitry (not shown) coupled to I/O pad 110), the negative effects of these parasitics attributable to ESD protection circuitry 120 become more pronounced.
It would be desirable to allow the ESD protection circuitry of a semiconductor device to remain large enough to handle typical ESD events while minimizing the effect of the parasitics caused by the ESD protection circuitry on a semiconductor device over a given range of operating frequencies.
Accordingly, an active inductance system and method is described that allows effective cancellation of the negative effect of parasitics caused by ESD protection circuitry over a range of frequencies on a semiconductor device. An impedance from an active inductance circuit may be transformed and reflected back to an I/O terminal of the semiconductor device. This impedance is designed to match the parasitics (e.g. parasitic capacitance) of the ESD protection circuitry.
An active inductance circuit according to the present invention may also be used to match the impedance of the signal source or load on I/O terminals of the semiconductor device. In one embodiment of the present invention, the active inductance circuit is programmably implemented, providing the capability to tune the characteristics of the active inductance circuit.
The present invention will be more fully understood in view of the following description and drawings.